The present invention relates a semiconductor device and a manufacturing technique for the same. Particularly, the present invention is concerned with a technique applicable effectively to a semiconductor device wherein electrode pads of a semiconductor chip and electrode pads of a wiring board are connected together through bonding wires.
As a semiconductor device there is known, for example, a semiconductor device called BGA (Ball Grid Array) type. The BGA type semiconductor device is of a package structure wherein a semiconductor chip is mounted on a main surface side of a wiring board called interposer and plural ball-like solder bumps as external connecting terminals are arranged on a back surface side opposite to the main surface side.
BGA type semiconductor devices of various structures have been developed and commercialized, but are broadly classified into those of a face-up bonding structure (wire bonding structure) and those of a face-down bonding structure. In the face-up bonding structure, electrode pads arranged on a main surface (circuit-forming surface) of a semiconductor chip and electrode pads arranged on a main surface of a wiring board are electrically connected together through bonding wires. In the face-down bonding structure, electrode pads arranged on a main surface of a wiring board and electrode pads arranged on a main surface of a semiconductor chip are electrically connected together through salient electrodes (e.g., solder bumps or stud bumps) interposed between those electrode pads.
A BGA type semiconductor device of the face-up bonding structure is disclosed, for example, in Japanese Unexamined Patent Publication No. 2001-144214. A BGA type semiconductor device of the face-down bonding structure is disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 6 (1994)-34983.
In connection with a wire bonding method wherein plural electrode pads arranged along one side of a main surface of a semiconductor chip and plural electrode pads arranged in two rows on a main surface of a wiring board and along one side of the semiconductor chip are electrically connected together through plural bonding wires, a technique for avoiding interference between pre-formed wires and a capillary is disclosed in Japanese Unexamined Patent Publication No. 2003-31610.
[Patent Literature 1]                Japanese Unexamined Patent Publication No. 2001-144214        
[Patent Literature 2]                Japanese Unexamined Patent Publication No. Hei 6 (1994)-34983        
[Patent Literature 3]                Japanese Unexamined Patent Publication No. 2003-31610        